Fabrication of field emission Si-tip array using reduced submicron masks generated by isotropic etching of mask patterns

Citation
Dw. Kim et al., Fabrication of field emission Si-tip array using reduced submicron masks generated by isotropic etching of mask patterns, MICROEL ENG, 46(1-4), 1999, pp. 423-426
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONIC ENGINEERING
ISSN journal
01679317 → ACNP
Volume
46
Issue
1-4
Year of publication
1999
Pages
423 - 426
Database
ISI
SICI code
0167-9317(199905)46:1-4<423:FOFESA>2.0.ZU;2-E
Abstract
We have developed a novel technique for fabricating submicron size mask pat terns using a wet etching technique of SiO2. The overetching of the SiO2 ma sk layer would present reduction of the diameters of the mask. The reductio n of 2 mu m SiO2 mask down to 0.5 mu m diameter will be presented and utili zed for the fabrication of nano-size Si-tip array. The 4 inch Si (100) wafe r was thermally oxidized and followed by the pattern transfer of original m ask patterns on the thermally grown oxide using conventional photographic c ontact printing method. The coated photoresist (PR) layer with 2 mu m thick ness was exploited as an etch mask layer for following mask reduction proce dure. The mask reduction procedure was performed using 7:1 buffered hydrofl uoric acid (BHF). Initially, the patterned PR mask layer was dipped into BH F solution for about 300 seconds in order to remove the SiO2 layer until th e Si substrate would be exposed. Additional similar to 300 second extra-dip ping in BHF solution created considerable overetching and resulted in the s maller diameter than that of the original one. The repetition of the dippin g process with precise control provided proper size of mask layers. The sha pe of the mask layer is found to have smaller diameter at the top and great er diameter at the bottom of the mask layer. Further experiments resulted i n the various submicron size SiO2 mask patterns. The diameters of the reduc ed masks were measured by scanning electron microscopy (SEM) and observed, for example, to be 0.3, similar to 0.2 mu m on the top and 0.7, 0.5 mu m at the bottom, respectively. The isotropic and anisotropic Si reactive ion et ching (RIE) was performed with this patterned wafer in order to provide sha rp Si tip on the similar to 2 mu m height Si-post arrays with the post diam eter down to similar to 0.2 mu m. The sharpening oxidation followed by oxid e etching resulted in the successful fabrication of the nanosize Si-tip arr ays.