Mapping and scheduling for heterogeneous architectures

Extensive and computationally complex signal processing and control applica tions are commonly constructed from small computational blocks where the lo ad decomposition and balance may not be easily achieved. This requires the development of mapping and scheduling strategies based on application to pr ocessor matching. In this context several application algorithms are utilis ed and investigated in this work within the development framework (DF) appr oach. The DF approach supports the specification, design and implementation of real-time control systems. It also contains several mapping and schedul ing tools to improve the performance of systems as well as tools for code g eneration. To improve the performance of an application, a new approach, na mely the priority-based genetic algorithm (PBGA), is developed and reported in this article. The approach is applied to several applications using par allel and distributed heterogeneous architectures and its performance verif ied in comparison to several previously developed strategies. (C) 1999 Else vier Science B.V. All rights reserved.