Stress-induced leakage current in p(+) poly MOS capacitors with poly-Si and Poly-Si0.7Ge0.3 gate material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p(+) polycrystalline silicon (poly-Si) and polycr ystalline Silicon-Germanium (poly-Si0.7Ge0.3) gate on 5.6-nm thick gate oxi des has been investigated, It is shown that the SILC characteristics are hi ghly asymmetric with gate bias polarity, This asymmetric behavior is explai ned by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low f ields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC, At positive gate bias, reduced SIL C is observed for poly-SiGe gates compared to poly-Si gates, This is most l ikely due to a lon er concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very i nteresting gate material for nonvolatile memory devices.