Drivability improvement on deep-submicron MOSFET's by elevation of source drain regions

Deep submicron MOSFET's with elevated source/drain (S/D) structures, where S/D extension regions were partially elevated besides deep S/D regions, wer e fabricated by use of Si selective epitaxial growth technique. As fairly c ompared with a well-developed conventional MOSFET, we clarify an advantage of the elevated S/D structures, i.e., improvement upon driving performance with keeping excellent short-channel characteristics, which is enhanced for decrease in gate sidewall spacer width. The experimental results are expla ined in terms of the reduction in S/D parasitic resistance by addition of t he Si epitaxial layer where the impurity profile is suitable.