A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications

The design of a high-resolution, high-speed, delta-sigma analog-to-digital converter that operates from a single 3.3-V supply is presented, This suppl y voltage presents several design problems, such as reduced signal swing an d nonzero switch resistance in the switched-capacitor circuits, These probl ems are tackled in this design by a careful optimization at the system leve l and by a detailed analysis of several circuit nonidealities, The converter uses a 2-1-1 cascade topology with optimized coefficients, Fo r an oversampling-ratio of only 24, the converter achieves a signal-to-nois e ratio of 87 dB, a signal-to-(noise + distortion) ratio of 82 dB, and an i nput dynamic range of 15 bits after comb filtering, The converter is sample d at 52.8 MHz, which results in the required signal bandwidth for asymmetri cal digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-mu m CMOS technology, in a 5-mm(2) die area, and consumes 200 mW from a 3.3-V power supply.