A 1-Gb/s, 0.7-mu m CMOS optical receiver with full rail-to-rail output swing

This paper presents a 1-Gb/s optical receiver with full rail-to-rail output swing realized in a standard 0.7-mu m CMOS technology. The receiver consis ts of a 1-k Omega transimpedance preamplifier followed by a postamplifier b ased on a biased inverter chain. The latter performs both a linear and a li miting amplification. The automatic biasing of the chain is provided throug h an offset tolerant replica circuit. The receiver requires no external com ponents or biasing voltages, It is designed for a relatively large 0.8-pF i nput capacitance and is fed from a single 5-V power supply. These propertie s make the circuit suitable for a commercial environment. A sensitivity of 10 mu A was measured at 1 Gb/s, The complete receiver, including all biasin g and replicas, consumes approximately 100 mW from the 5-V supply. When pow ered from a 3.3-V supply, a maximal bit rate of 600 Mb/s is achieved, while the power consumption is reduced to approximately 26.5 mW.