A low-power and high-performance CMOS fingerprint sensing and encoding architecture

A CMOS fingerprint sensor architecture with embedded cellular logic for ima ge processing is presented. The system senses a fingerprint image with a ca pacitive technique and performs several image-processing algorithms, includ ing thinning the ridges of the fingerprint structure and encoding it to its characteristic features. Image processing is achieve ed by application of hexagonal local operators implemented in pixel-parallel mixed neuron-MOS/CM OS logic circuits. The massive parallelism of the architecture leads to a v ery low power dissipation. Results of simulations and measurements on a dem onstrator chip in 0.65-mu m double-poly standard CMOS technology are shown. The approach is well suited for person-identification applications, especi ally in small and low-cost portable systems, such as smart cards.