A real-time digital VCR encode decode and MPEG-2 decode LSI implemented ona dual-issue RISC processor

A real-time system large-scale-integrated circuit (LSI) for digital video c assette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemente d on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performanc e and can execute fixed-length data processing at the block level as well a s processing at the macro-block level and above for the DVCR/MPEC-2, The de dicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables, The dedicated hardware for video-block loading can process video-block data tra nsfers with half-pel operations, The LSI size is 7.7 x 7.2 mm(2) in a 0.25- mu m process.