A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

Citation
K. Washio et al., A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay, IEEE DEVICE, 46(7), 1999, pp. 1411-1416
Citations number
13
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
46
Issue
7
Year of publication
1999
Pages
1411 - 1416
Database
ISI
SICI code
0018-9383(199907)46:7<1411:ASSHWS>2.0.ZU;2-Q
Abstract
An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bip olar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-mu m-wide SiGe b ase self-aligned to the 0.1-mu m-wide emitter was selectively grown by usin g a UHV/CVD system, This self-aligned structure effectively reduces collect or capacitance. In SMI technology, a tungsten film is selectively stacked o n all poly-Si electrodes (base, emitter, and collector) in a self-aligned m anner by using selective deposition without any heat treatment. So this tec hnology does not cause unwanted diffusion of the base dopants and keeps a s hallow intrinsic base profile. SMI technology can therefore provide low par asitic resistances and is well-suited to an SiGe-base HBT, A 2-mu m-wide BP SG/SiO2 refilled trench was introduced in order to reduce the substrate cap acitance, The low dielectric constant of BPSG/SiO2 and the wide trench are very effective in reducing the sidewall element of substrate capacitance. T his technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit.