Physically-based threshold voltage determination for MOSFET's of all gate lengths

Citation
M. Tsuno et al., Physically-based threshold voltage determination for MOSFET's of all gate lengths, IEEE DEVICE, 46(7), 1999, pp. 1429-1434
Citations number
17
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
46
Issue
7
Year of publication
1999
Pages
1429 - 1434
Database
ISI
SICI code
0018-9383(199907)46:7<1429:PTVDFM>2.0.ZU;2-4
Abstract
A reliable method to determine the threshold voltage V-th for MOSFET's with gate length down to the sub-0.1 mu m region is proposed. The method determ ines V-th by linear extrapolation of the transconductance g(m) to zero and is therefore named "GMLE method." To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulat ion was applied. The results reveal that determined V-th values always meet the threshold condition, i.e., the onset of inversion layer buildup.