Deposited inter-polysilicon dielectrics for nonvolatile memories

Deposited instead of thermally grown oxides were studied to form very high- quality inter-polysilicon dielectric lavers for embedded nonvolatile memory application. It was found that by optimizing the microstructure, i.e,, tex ture and morphology of the polysilicon layers, and by optimizing the post d ielectric deposition anneal, very high-quality dielectric layers can be obt ained. In this paper it is shown on simple capacitor structure level and fu ll EEPROM device level that the electrical properties of interpol dielectri c layers can be improved tremendously by using deposited dielectric layers with additional rapid thermal anneal. Typical results are: a high charge-to -breakdown (Q(BD) approximate to 25 C/cm(2)). low leakage currents and decr eased charge trapping during constant current stress. An additional advanta ge is the low thermal budget, which is very attractive for embedded applica tions. However, results depend on the polysilicon preparation, dielectric t ype and RTP anneal environment. From electrical evaluation it appeared that even for deposited dielectric l ayers the influence of polysilicon surface roughness and corners is conside rable, The optimized combination of flat polysilicon layers, deposited inter-polys ilicon dielectric and additional optimized rapid thermal anneal have been a pplied in full EEPROM devices. Cycling over one million cycles was possible , which indicates an endurance improvement by a factor of 10.