The impact of high-kappa gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's

The potential impact of high-K gate dielectrics on device short-channel per formance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by th e fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectri c thickness-to-length aspect ratio is a proper parameter to quantify. the p ercentage of the fringing field acid thus the short channel performance deg radation, In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. U sing double-layer gate stack structures and low-K dielectric as spacer mate rials can well confine the electric fields within the channel thereby minim izing short-channel performance degradation. The introduction of a metal ga te not only eliminates the poly gate depletion effect, but also improves sh ort-channel performance. Several approaches have been proposed to adjust th e proper threshold voltage when midgap materials or metal gates are used.