A 130-nm channel length partially depleted SOICMOS-technology

A partially depleted silicon-on-insulator (PDSOI) CMOS technology employing pocket implantation and a self-aligned titanium silicidation with an effec tive gate length of 0.13 mu m has been developed. An advanced mesa isolatio n process is used to suppress corner devices, A clear improvement of the de vice performance due to the novel isolation process is shown. Good transfer characteristics with a steep subthreshold slope and an excellent roll-off of threshold voltage is obtained for both nMOS and pMOS devices down to eff ective gate lengths of 0.13 mu m, A 10k transistor circuit which is mostly combinatoric (carry select adder circuit) has been realized and characteriz ed as a performance test circuit with an effective gate length of 0.18 mu m and shows high performance and low power consumption compared to an optimi zed 0.18 mu m effective gate length bulk technology with similar processing .