The development and validation of fault-tolerant computers for critical rea
l-time applications are currently both costly and time consuming. Often, th
e underlying technology is out-of-date by the time the computers are ready
for deployment. Obsolescence can become a chronic problem when the systems
in which they are embedded have lifetimes of several decades. This paper gi
ves an overview of the work carried-out in a project that is tackling the i
ssues of cost and rapid obsolescence by defining a generic fault-tolerant c
omputer architecture based essentially on commercial off-the-shelf (COTS) c
omponents (both processor hardware boards and real-time operating systems).
The architecture uses a limited number of specific, but generic, hardware
and software components to implement an architecture that can be configured
along three dimensions: redundant channels, redundant lanes, and integrity
levels. The two dimensions-of physical redundancy allow the definition of
a wide variety of instances with different fault tolerance strategies. The
integrity level dimension allows application components of different levels
of criticality to coexist in the same instance. The paper describes the ma
in concepts of the architecture, the supporting environments for developmen
t and validation, and the prototypes currently being implemented.