An efficient architecture for the in-place fast cosine transform

Citation
M. Sanchez et al., An efficient architecture for the in-place fast cosine transform, J VLSI S P, 21(2), 1999, pp. 91-102
Citations number
21
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
ISSN journal
13875485 → ACNP
Volume
21
Issue
2
Year of publication
1999
Pages
91 - 102
Database
ISI
SICI code
1387-5485(199906)21:2<91:AEAFTI>2.0.ZU;2-H
Abstract
The two-dimensional discrete cosine transform (2D-DCT) is at the core of im age encoding and compression applications. We present a new architecture fo r the 2D-DCT which is based on row-column decomposition. An efficient archi tecture to compute the one-dimensional fast direct (1D-DCT) and inverse cos ine (1D-IDCT) transforms, which is based in reordering the butterflies afte r their computation, is also discussed. The architectures designed exploit locality, allowing pipelining between stages and saving memory (in-place). The result is an efficient architecture for high speed computation of the ( 1D, 2D)-DCT that significantly reduces the area required for VLSI implement ation.