Synthesis of embedded software from synchronous dataflow specifications

The implementation of software for embedded digital signal processing (DSP) applications is an extremely complex process. The complexity arises from e scalating functionality in the applications; intense time-to-market pressur es; and stringent cost, power and speed constraints. To help cope with such complexity, DSP system designers have increasingly been employing high-lev el, graphical design environments in which system specification is based on hierarchical dataflow graphs. Consequently, a significant industry has eme rged for the development of data-flow-based DSP design environments. Leadin g products in this industry include SPW from Cadence, COSSAP from Synopsys, ADS from Hewlett Packard, and DSP Station from Mentor Graphics. This paper reviews a set of algorithms for compiling dataflow programs for embedded D SP applications into efficient implementations on programmable digital sign al processors. The algorithms focus primarily on the minimization of code s ize, and the minimization of the memory required for the buffers that imple ment the communication channels in the input dataflow graph. These are crit ical problems because programmable digital signal processors have very limi ted amounts of on-chip memory, and the speed, power, and cost penalties for using off-chip memory are often prohibitively high for embedded applicatio ns. Furthermore, memory demands of applications are increasing at a signifi cantly higher rate than the rate of increase in on-chip memory capacity off ered by improved integrated circuit technology.