Threshold voltage model for deep-submicron fully depleted SOI MOSFETs withback gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully deplete d SOI MOSFETs has been derived. The model is based on the analytical soluti on of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Po isson's equation and the short-channel solution to the Laplace equation, an d the solution of the Poisson's equation in the silicon substrate (back sil icon). The proposed model accounts for the effects of the back gate substra te induced surface potential at the buried oxide-substrate interface which contributed an additional 15-30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage rang e are determined upon which the surface potential at the buried oxide-subst rate interface is accumulated, depleted, or inverted. The short-channel ass ociated drain induced barrier lowering effects are also included in the mod el. The model predications are in close agreement with PISCES simulation re sults. The equivalence between the present model and previously reported mo dels is proven. The proposed model is suitable for use in circuit simulatio n tools such as Spice. (C) 1999 Elsevier Science Ltd. All rights reserved.