Time-domain model for power dissipation of CMOS buffers driving lossy lines

The dynamic power consumption of a CMOS buffer driving lossless and lossy t ransmission lines is investigated. A time-domain model for power dissipatio n in both the line driver and the interconnect losses is also presented. Th e model fully agrees with HSPICE simulations and is particularly suitable f or implementation in CAD tools for fast estimation of VLSI dissipation circ uits.