Efficient method for simulating time delays of distributed interconnections in VLSI circuits

Authors
Maffezzoni, P Brambilla, A
Citation
P. Maffezzoni et A. Brambilla, Efficient method for simulating time delays of distributed interconnections in VLSI circuits, ELECTR LETT, 35(12), 1999, pp. 976-977
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
35
Issue
12
Year of publication
1999
Pages
976 - 977
Database
ISI
SICI code
0013-5194(19990610)35:12<976:EMFSTD>2.0.ZU;2-0
Abstract
A new technique is described for modelling a general distributed RC line th rough a simple lumped net. This reduced order model approximates both the l ong time voltage response and the input loading effect of the line. The pro posed method has the advantage of allowing the employment of circuit simula tors such as SPICE to evaluate interconnect delays in complex layouts.