A design hierarchy of IC interconnects and gate patterns

A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate pattern s at a CMOS cell level and multilevel interconnect scheme at a chip level a re proposed. This approach generates the layout design rules of gate patter ns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of t echnology development.