Analog CMOS implementation of quantized interconnection neural networks for memorizing limit cycles

In order to investigate the dynamic behavior of quantized interconnection n eural networks on neuro-chips, we have designed and fabricated hardware neu ral networks according to design rule of a 1.2 mu m CMOS technology. To thi s end, we have developed programmable synaptic weights for the interconnect ion with three values of +/- 1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.