Buffer memory requirements in DSP applications

In this paper, we study consistent synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the con struction of a deadlock-free static schedule. A graph is split up in chains and clusters that can be studied independently. We present the results for chains, as well as for the most frequent clusters. The results will be use d in the rapid prototyping environment GRAPE-II in case the emulation hardw are contains FPGAs, or when memory is critical.