Test and diagnosis of faulty logic blocks in FPGAs

Field programmable gate arrays (FPGAs) have been used in many areas of digi tal design. Because FPGAs are programmable, faults in them can be easily to lerated once fault sites are located. However, diagnosis of faults in FPGA has not yet been explored by researchers. A new methodology for the testing and diagnosis of faults in FPGAs is presented, based on built-in self-test . The proposed method imposes no hardware overhead, and requires minimal su pport from external test equipment. Test time depends only on the number of faults, and is independent of the chip size. With the help of this techniq ue, chips with faults can still be used. As a result, the chip yield can be improved and chip cost is reduced. This method can also be used in fault-t olerant systems, in which a good functional circuit can still be mapped to a. FPGA with faulty elements, as long as the fault sites are known.