Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors

A low-voltage BICMOS four-quadrant multiplier using triode-region transisto rs is presented. This circuit has been fabricated in a 1.0-mu m BiCMOS proc ess. Experimental results show that for a power supply of +/-1.5 V, the lin ear range is over +/-0.6 V with the linearity error of less than 2%. The to tal harmonic distortion is less than 2% with an input range up to +/-0.6 V, The measured -3-dB bandwidth of this proposed BiCMOS multiplier is about 1 0 MHz. This circuit is expected to be useful in low-voltage analog signal-p rocessing applications.