4-channel rad-hard delay generation ASIC with 1ns timing resolution for LHC

An ASIC was developed to precisely delay digital signals within the range o f 0-24ns in steps of Ins. To obtain well defined delay values independent o f variations in process, supply voltage and temperature, four independent d elay channels are controlled by a common control voltage derived from a del ay-locked loop (DLL), which is synchronized to an external 40 MHz clock sig nal. The delay values of the four signal channels and the clock channel can be individually programmed via an (IC)-C-2 interface. Due to an automatic reset logic the chip does not need an external reset signal. A first versio n of the chip was developed in a non-rad-hard 0.8 mu m technology and the s uccessful prototype was then transferred to a radiation hard process (DMILL ). Measurement results for both chip variants will be presented.