On robust two-pattern testing of one-dimensional CMOS iterative logic arrays

Authors
Gizopoulos, D Paschalis, A Nikolos, D Halatsis, C
Citation
D. Gizopoulos et al., On robust two-pattern testing of one-dimensional CMOS iterative logic arrays, INT J ELECT, 86(8), 1999, pp. 967-978
Citations number
16
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
INTERNATIONAL JOURNAL OF ELECTRONICS
ISSN journal
00207217 → ACNP
Volume
86
Issue
8
Year of publication
1999
Pages
967 - 978
Database
ISI
SICI code
0020-7217(199908)86:8<967:ORTTOO>2.0.ZU;2-Y
Abstract
In this paper a graph model and a method to construct robust (for the first time in open literature) as well as non-robust two-pattern tests for one-d imensional iterative logic arrays (ILAs) are presented. Exploring the graph structure we can find two-pattern tests that can be applied with a constan t or linear number of test vectors to all the ILA cells. Such tests are sub sequently characterized as robust or non-robust two-pattern tests.