A Salicide-Bridged trench capacitor with a Double-Sacrificial-Si3N4-Sidewall (DSS) for high-performance logic-embedded DRAMs

Authors
Togo, M Nobusawa, H Hamada, M Yoshida, K Tanigawa, T
Citation
M. Togo et al., A Salicide-Bridged trench capacitor with a Double-Sacrificial-Si3N4-Sidewall (DSS) for high-performance logic-embedded DRAMs, NEC RES DEV, 40(3), 1999, pp. 277-281
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
NEC RESEARCH & DEVELOPMENT
ISSN journal
0547051X → ACNP
Volume
40
Issue
3
Year of publication
1999
Pages
277 - 281
Database
ISI
SICI code
0547-051X(199907)40:3<277:ASTCWA>2.0.ZU;2-3
Abstract
We propose a Double-Sacrificial-Si3N4-Sidewall (DSS) technology to develop a Salicide-Bridged trench-capacitor cell for high-performance logic-embedde d DRAMs. Both the DSS technology and the Salicide-Bridging are fully compat ible with high-performance CMOS processes. With these technologies, a stora ge node of a Substrate-Plate Trench (SPT) capacitor can be connected to a d rain node even over a thick oxide collar during the silicidation.