Merits of CMOS SIMOX technology for low-voltage SRAM macros

Citation
K. Kumagai et al., Merits of CMOS SIMOX technology for low-voltage SRAM macros, NEC RES DEV, 40(3), 1999, pp. 287-291
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
NEC RESEARCH & DEVELOPMENT
ISSN journal
0547051X → ACNP
Volume
40
Issue
3
Year of publication
1999
Pages
287 - 291
Database
ISI
SICI code
0547-051X(199907)40:3<287:MOCSTF>2.0.ZU;2-V
Abstract
A 128-kbit SRAM (Static Random Access Memory) macro with the 0.35 mu m FD ( Fully-Depleted)-CMOS/SIMOX (Separation by Implantation of Oxygen) technolog y has been developed to demonstrate the merits of that technology for the l ow-voltage applications. Its access time at Vdd=1.5V was comparable with th at obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3V, d ue to the combination of the small S/D capacitance and the small back-bias effect. As the yield of the 128-kbit SRAM: macros was almost the same as th e standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD- CMOS/SIMOX technology has also been demonstrated.