DC voltage-voltage method to measure the interface traps in sub-micron MOSTs

A dc voltage-voltage technique for the measurement of stress-generated inte rface traps in submicron MOSTs is demonstrated. This method uses the source -bulk-drain of a submicron MOST as an effective lateral bipolar transistor when the channel region is out of inversion under the control of the gate v oltage V-gb. The emitter injects the minority carriers to the base region a nd the collector is open. The V-cb versus V-gb spectrum can be explained qu antitatively in the spirit of the extended Ebers-Moll equations and interfa ce trap SRH recombination. The spectrum shows clear information on stress-g enerated interface traps located at the collector-junction region. The new method has the advantages of simplicity, high sensitivity and wide applicat ion range to different device structures. A single effective interface trap at the source or drain side could be detected, and interface traps at the source side can be separated from those at the drain side by the new method . Moreover, we propose an improved gated-diode method to separate interface traps at the source side from those at the drain side.