Preparation of silicon-on-gallium arsenide wafers for monolithic optoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (approximate to 100 nm) single-crystal si licon layers on oxide-coated gallium arsenide wafers for use in optoelectro nic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolith ic integration of thick, stress sensitive optoelectronic devices on silicon , without compromising the performance of CMOS circuitry which can be fabri cated in very thin, compressively strained silicon layers using SOI techniq ues.