Estimation of ground bounce effects on CMOS circuits

Ground bounce estimation is important to determine the impact of simultaneo us switching of input/output (I/O) drivers and clock drivers on the perform ance of application-specific integrated circuits (ASIC's), In this paper, w e develop models to estimate the peak and damped resonance noise of the gro und and power bounce. These models are developed for both long and short ch annel devices. Comparison with H-simulation program with integrated circuit emphasis (HSPICE) simulation indicates a good match. These models are simp le and suitable for hand calculation.