Configuration compression for the Xilinx XC6200 FPGA

One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedup s possible in this exciting new paradigm, In this paper we explore one tech nique for reducing this overhead: the compression of configuration datastre ams. We develop an algorithm, targeted to the decompression hardware imbedd ed in the Xilinx XC6200 series field-programmable gate array architecture, that can radically reduce the amount of data needed to transfer during reco nfiguration. This results in an overall reduction of about a factor of four in total bandwidth required for reconfiguration.