MEPHISTO - a 128-channel front end chip with real time data sparsificationand multi-hit capability

The MEPHISTO chip uses a novel binary architecture to achieve a highspeed r eadout for multichannel detectors, like silicon strip detectors or MSGCs. T he architecture is an alternative to existing designs with raw data pipelin es as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hit s per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high ra tes is also possible. The occupied chip area depends on the average data ra te which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (C) 199 9 Elsevier Science B.V. All rights reserved.