Design of a sub-1.5 v, 20 MHz, 0.1% MOS current-mode sample-and-hold circuit

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1.5 V supply voltage, 20 MHz clock frequen cy, and less than 0.1% linearity. A newly developed voltage-to-current conv erter suppresses the voltage change at an input terminal and achieves low-v oltage operation with superior linearity. Sample switches are differentiall y placed at the inputs of a differential amplifier so that the feed through errors from switches cancel out. The MOS current mode S/H circuit is desig ned and simulated using CMOS 0.6 mu m device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0.1%, and 1 MHz input from a 1.5 V power supply is achievable.