The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

This brief proposes a new architecture for the oversampling delta-sigma ana log-to-digital converter (ADC) utilizing a voltage-controlled oscillator (V CO). The VCO, associated with a pulse counter, works as a high-speed quanti zer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the inpu t voltage. If the maximum VCO frequency (fvm) is designed in the range of ( 2(bq) - 2)fos < fvm < (2(bq)-1)fos and a bq-bit counter is used, a multibit (bq-bit) quantizer can be realized, where fos is the oversampling frequenc y. The performance of the proposed converter is evaluated using a functiona l simulation. A 59-dB SNR at a 5-MHz bandwidth is obtained with fos = 400 M Hz, even in the case of a 1-bit quantizer. The multibit quantizer using a h igh-frequency VCO significantly improves an SNR and signal bandwidth. This architecture is highly suitable for implementation with deep sub-mu m CMOS devices, which can attain improved switching speeds and reduce power dissip ation during Low voltage operation. It provides wideband oversampling ADC f or video and wireless signals and a low voltage system-on-a-chip solution f or multimedia applications.