Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-angstrom gate oxide MOSFET's

Citation
K. Ahmed et al., Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-angstrom gate oxide MOSFET's, IEEE DEVICE, 46(8), 1999, pp. 1650-1655
Citations number
23
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
46
Issue
8
Year of publication
1999
Pages
1650 - 1655
Database
ISI
SICI code
0018-9383(199908)46:8<1650:IOTCAC>2.0.ZU;2-N
Abstract
This paper discusses the limitations on MOSFET test structures used in extr acting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-Angstrom oxide MOS devices, transistors with channel lengths le ss than about 10 mu m will be needed to avoid an extrinsic capacitance roll -off in strong inversion. The upper limit of the channel length has been es timated using a new simple transmission-line-model of the terminal capacita nce, which accounts for the nonnegligible gate tunneling current and finite channel resistance.