Monitoring of stress reduction in shallow trench isolation CMOS structuresvia synchrotron X-ray topography, electrical data and raman spectroscopy

Local oxidation of silicon (LOCOS) isolation technology is becoming increas ingly unusable for critical dimensions of 0.25 mu m and below, due to the i ntolerably large dimension of the oxide "bird's beak". Therefore, this tech nique has been replaced by a process called shallow trench isolation (STI) which uses deposited dielectrics to fill trenches etched in the silicon bet ween the active areas. One of the chief drawbacks to STI is the tendency of such structures to be highly stressed, especially after the oxide/dielectr ic backfill, which can have a deleterious impact on the electrical performa nce of fabricated devices. It is essential to monitor the stress/strain fie lds generated by shallow trench isolation structures. Synchrotron X-ray top ography (SXRT), a genuinely non-destructive technique, has been employed to provide in situ stress evaluation during the development of an STI-based c omplimentary metal oxide semiconductor (CMOS) integrated circuit process. V arious process options were evaluated and the data was compared with electr ical n(+)/p diode leakage and micro-Raman spectroscopy data.