Energy-recovery flip-flop design using improved adiabatic pseudo-domino logic structure

Adiabatic or energy-recovery logic families have been reported in the liter ature for low-power applications (A.G. Dickinson, J.S. Denker, Adiabatic dy namic logic, IEEE Journal of Solid-State Circuits 30(3) (1995) 311-315; D. Maksimovic, V.G. Oklobdzija, Clocked CMOS adiabatic logic with single AC po wer supply, in: Proceedings of the Twenty-First European Solid-State Circui ts Conference, 1995, pp. 370-373; Y. Moon, D.K. Jeong, An efficient charge recovery logic circuit, IEEE Journal of Solid-State Circuits 31(4) (1996) 5 14-522; W.Y. Wang, K.T. Lau, Adiabatic pseudo-domino logic, Electronics Let ters 31(23) (1995) 1982-1983; K.T. Lau, F. Liu, Improved adiabatic pseudo-d omino logic family, Electronics Letters 33(25) (1997) 2113-2114; K.T. Lau, F. Liu, Four-phase improved adiabatic pseudo-domino logic, Electronics Lett ers 34(4) (1998) 343-344; S.M. Yoo, S.M. Kang, A bootstrapped NMOS charge r ecovery logic, in: Proceedings of the IEEE Great Lakes Symposium on VLSI, 1 998, pp. 30-33). These designs have concentrated on combinational logic. In this article, SR flipflop and JK flip-flop designs based on the Improved A diabatic Pseudo-Domino Logic (IAPDL) circuit structure and the auxiliary cl ocking system of the IAPDL-4 phi (four-phase IAPDL) are presented. Besides the reduced transistor count, HSPICE simulations performed indicate signifi cant improvement in terms of power consumption over CMOS transmission gate- based flip-flops. (C) 1999 Elsevier Science Ltd. All rights reserved.