Mixed serial-parallel sensing scheme for a 64-Mbit 4-bit/cell factory-programmed OTP-ROM

This article presents a sensing scheme for multilevel (ML) non-volatile mem ories. Sensing is accomplished following a mixed serial-parallel approach: a memory cell is read according to a binary-search algorithm where each sea rch step carries out a given number of simultaneous comparisons between its content and adequate references. Two sensing steps, each performing three parallel comparisons, are able to detect as many as 4 bits per cell (16 lev els). Only three sense amplifiers are required per each cell to be read sim ultaneously. To obtain tight current distributions (within 3 mu A) for the programmed states, as required for safely storing and sensing 4 bits per ce ll, a highly-parallel ML factory-programming technique for one-time program mable ROMs is used. Simulated access time for a 16-level-cell 64-Mbit devic e in a mature double-poly single-metal 0.4 mu m CMOS EPROM technology is si milar to 120 ns when using 3 V power supply. (C) 1999 Elsevier Science Ltd. All rights reserved.