Gigabit-per-second, ECL-compatible I/O interface in 0.35-mu m CMOS

This paper presents high-speed differential input and output (I/O) interfac e circuits for gigabit-per-second serial data communication. The circuits a re implemented in a 3.3-V/0.35-mu m CMOS process. Signal levels are compati ble with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A diffe rential open-drain circuit with pulsed bias and active pullups offers signi ficantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicro meter technology, the presented I/O blocks enable a full-CMOS chip to commu nicate with highspeed ECL-compatible systems and ease up a common I/O-relat ed speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous perfor mance of the receiver and the transmitter was tested at rates up to 2.5 Gb/ s.