Optimization of word-line booster circuits for low-voltage flash memories

Two word-line booster circuits, which output a word-line voltage for readin g dash memory data, are analyzed and optimized. A capacitor-switched booste r circuit outputs a voltage higher than the supply voltage by switching the connection state of one or more boosting capacitors with the load capacito r from parallel to series. The optimum number of capacitors and Capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current cons umed by the boosting operation is also analytically derived. In addition, a nother booster circuit-Dickson charge-pump circuit-is optimized under the c ondition to maximize the output current at a high word-line voltage. Charac teristics of the booster circuits are compared, and the selection of booste r circuit for low-voltage flash memory is discussed.