High-performance RISC microprocessors

Authors
Choquette, J Gupta, M McCarthy, D Veenstra, J
Citation
J. Choquette et al., High-performance RISC microprocessors, IEEE MICRO, 19(4), 1999, pp. 48-55
Citations number
3
Categorie Soggetti
Computer Science & Engineering
Journal title
IEEE MICRO
ISSN journal
02721732 → ACNP
Volume
19
Issue
4
Year of publication
1999
Pages
48 - 55
Database
ISI
SICI code
0272-1732(199907/08)19:4<48:HRM>2.0.ZU;2-2
Abstract
TWO MIPS CORES BASED ON THE MONTAGE ARCHITECTURE SUPPORT THE NEEDS OF EMBED DED SYSTEMS ANO CONSUMER APPLIANCES. THE FLEXIBILITY OF THE ARCHITECTURE PE RMITS EXTENSIONS TO BE RAPIDLY IMPLEMENTED TO MEET DEMANDING CUSTOMER REQUI REMENTS.