A floating point multiplier performing IEEE rounding and addition in parallel

In the conventional floating point multipliers, the rounding stage is usual ly constructed by using a high speed adder for the increment operation, inc reasing the overall execution time and occupying a large amount of chip are a. Furthermore, it may accompany additional execution time and hardware com ponents for renormalization which may occur by an overflow from the roundin g operation. A floating-point multiplier performing addition and IEEE round ing in parallel is designed by optimizing the operational flow based on the characteristics of floating point multiplication operation. A hardware mod el for the floating point multiplier is proposed and its operational model is algebraically analyzed in this research. The floating point multiplier p roposed does not require any additional execution time nor any high speed a dder for rounding operation. In addition, the renormalization step is not r equired because the rounding step is performed prior to the normalization o peration. Thus, performance improvement and cost-effective design can be ac hieved by this approach. (C) 1999 Elsevier Science B.V. All rights reserved .