Hardware realization of a java virtual machine for high performance multimedia applications

This paper describes a new architecture for JAVA-based, interactive multime dia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows the direct execution of Java bytecode. In a sing le clock cycle, up to 3 bytecode instructions can be decoded and executed i n parallel using a RISC pipeline. A splitable 64-bit ALU implementation add resses demanding processing requirements of typical multimedia signal proce ssing schemes. The on-chip caches are adapted to the specific data structur es of the JVM. The proposed architecture supports execution of multiple Jav a threads in parallel. An implementation of basic building blocks of the pr ocessor with a standard-cell library provides an estimate of 150 MHz clock- speed for a 0.35 mu m 3 metal layer CMOS process. With a size of less than 10 mm(2) needed for the core logic, it is possible to integrate multiple JV Ms together with larger cache memories on a single chip. Based on these res ults, we discuss various performance aspects of JAVA for use in future mult imedia terminals.