Low-power parallel video compression architecture for a single-chip digital CMOS camera

A low-power, large-scale parallel video compression architecture for a sing le-chip digital CMOS camera is discussed in this paper. This architecture i s designed for highly computationally intensive image and video processing tasks necessary to support video compression. Two designs of this architect ure, an MPEG2 encoder and a DV encoder, are presented. At an image resoluti on of 640 x 480 pixels (MPEG2) and 720 x 576 (DV) and a frame rate of 25 to 30 frames per second, a computational throughput of up to 1.8 billion oper ations per second (BOPS) is required. This is supported in the proposed arc hitecture using a 40 MHz clock and an array of 40 to 45 parallel processors implemented in a 0.2 mu m CMOS technology and with a 1.5 V supply voltage. Power consumption is significantly reduced through the single-chip integra tion of the CMOS photo sensors, the embedded DRAM technology, and the propo sed pipelined parallel processors. The parallel processors consume approxim ately 45 mW of power resulting a power efficiency of 40 BOPS/W.