Subsetting behavioral intellectual property for low power ASIP design

Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruc tion subsetting and explores its use as a means of reducing power consumpti on from the system level of design. Instruction subsetting is defined as cr eating an application specific instruction set processor from a more genera l processor, such as a DSP. Although not as effective as an ASIC solution, instruction subsetting provides much of the power savings while maintaining some level of programmability. Beyond energy savings, instruction subsetti ng also offers the opportunity to reduce the design cycle through the re-us e of existing processor intellectual property including behavioral and stru ctural designs, hardware simulators, application code, and compilers. We sy nthesized 9 ASIPs through place and route and found that a poorly chosen in struction set may consume more than 4 times the energy of an ASIP with a pr oper instruction set choice. This finding will allow designers to consider another set of trade-offs in their hardware/software design space explorati on.