Energy-delay efficient data storage and transfer architectures and methodologies: Current solutions and remaining problems

Recent experiments for the realisation of data-dominated multi-media applic ations have clearly demonstrated that the main power (and largely also area ) cost is situated in the memory units and the (bus) communication hardware . On the custom hardware side, several system level memory management relat ed methodologies are being proposed which promise very large savings on pow er and also on area while still meeting the real-time constraints. Unfortun ately, on the software side these methodologies are not applicable as such. In order to alleviate this situation for systems-on-a-chip with a heteroge neous mix of processors, novel methodology and architecture approaches are required. In this research summary paper, the currently available solutions will be reviewed and some major problems to be solved in the future are id entified.