Error and flow control in terabit intelligent optical backplanes

The design of a free-space optical backplane which supports error and flow control functions is described, Traditionally, these functions are implemen ted in custom high-speed electronic application specific integrated circuit s, which are physically removed from the optical interconnect layer, In thi s paper, we consider migrating these functions directly into the optoelectr onic layer, yielding an "intelligent optical backplane." Conventional error control protocols are infeasible with optical backplanes since they requir e excessive amounts of hardware, The design of an efficient error control p rotocol based upon a multidimensional parity check, along with the effectiv e flow control protocol is proposed and analyzed. The key blocks of the pro tocol have been implemented in 0.8- and 0.5-mu m CMOS/SEED devices and are summarized. The protocols require significantly less hardware than alternat ive schemes, and smart pixel arrays supporting these protocols are scalable to higher bandwidths and lower latencies, A very large scale integration a nalysis indicates that using 2004 technology, a free-space backplane can po tentially be clocked at 1 GHz and support 24 Tb/s of bandwidth. Finally, th e proposed error control protocols should be useful in optical disks and ho lographic memory systems, which also perform error control on large two-dim ensional arrays of optical bits.