Clock-driven on-chip testing for superconductor logic circuits

We have developed and demonstrated a clock-driven on-chip testing (CDOT) me thod for high-speed testing of superconductor logic circuits. This testing method uses an on-chip signal-pattern generator (SPG) driven by a clock sig nal. The SPG is based on a feedback shift register, in which a complement o utput of the last-stage D-flip-flop is fed back to the first-stage D-flip-f lop. Thus, SPG generates a periodic signal-pattern when a clock signal is a pplied to it. The advantages of this testing method are that, a) no externa l control signal is needed; b) a simple SPG that consists of only D-flip-fl ops is used; c) it is easy to extend to multi-bit testing. This greatly sim plifies high-speed testing and design of test circuits. We have applied thi s method to the high-speed testing of the ring interface (RIF) circuit, whi ch is an elemental circuit in our superconducting ring-network system. We h ave designed a test circuit, consisting of the RIF circuit and a 12-bit on- chip test-pattern generator, with resistor-coupled Josephson logic (RCJL), The test circuit includes about 1,400 Josephson-junctions. It has been fabr icated using Nb/AlOx/Nb Josephson-junction technology. As the result of the high-speed testing, full operation of the RIF circuit at 1-GHz clock frequ ency and proper operation of a sending part of the RIF circuit at 2-GHz clo ck frequency have been successfully verified.