Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization

A mechanical polishing planarization (MPP) process is developed with an end point detection method. h-IPP makes it possible to form self-aligned contac ts on small junctions and to decrease parasitic inductance. It can also con trol the thickness of the insulation layers precisely. MPP was used to fabr icate a 22 mu m x 22 mu m vortex transitional memory cell and the cell oper ated correctly. The reliability of interlayer insulation was increased for 61-Kbit memory cell arrays fabricated using MPP. It is concluded that MPP i s an effective technology for fabricating high-density Josephson circuits.